An image sensor generally comprises a semiconductor substrate and an array of imaging elements arranged in horizontal rows and vertical columns. FIG. 1 shows a single imaging element U comprising a pixel P. The pixel comprises a photosensor PS, a transfer transistor TT, a reset transistor RT, a source-follower transistor FT, and an output transistor OT.
The photosensor PS has an anode connected to ground and a cathode coupled to a charge node N1 through the transfer transistor TT. The transfer transistor TT has a source S connected to the photosensor PS, a drain D connected to node N1, and a gate G driven by an activation signal SL. The reset transistor RT has a drain D receiving a supply voltage VS, a source connected to node N1, and a gate G driven by a pixel reset signal PR. The source-follower transistor FT has a gate G driven by node N1, a drain D receiving a supply voltage VS, and a source S connected to the drain D of the output transistor OT. The output transistor OT has a gate G driven by a row readout signal RR, and a source S connected to an output OUT of the pixel.
For each pixel, an image capture cycle comprises a reset phase, a charge accumulation phase, a charge transfer phase, and a signal read phase. During the reset phase, the transfer transistor TT is set in a conducting state, and couples the photosensor PS to node N1. Any charges accumulated in the photosensor since the last image capture cycle are transferred to node N1.
During the charge accumulation phase, the transfer transistor TT is set in a blocked state to isolate the photosensor PS. The pixel is exposed to an incident light, and electrical charges are generated in the photosensor PS. During this time, a voltage V1 at node N1 is first charged to the supply voltage via the reset transistor RT, then the node is isolated by setting the transistor RT in the blocked state. Voltage V1 drops to a reset voltage, which is sensed by the source-follower transistor FT and supplied via the output transistor OT to an image processing system (not shown), for storage.
During the charge transfer phase, the transfer transistor TT is again set in the conducting state, and charges accumulated in the photosensor PS are transferred to node N1. Voltage V1 goes to a signal read voltage depending on the amount of charges accumulated.
During the signal read phase, the source-follower transistor FT senses the signal read voltage and supplies it to the image processing system via the output transistor OT. In a process known as Correlated Double Sampling, the difference between the reset voltage and the signal read voltage is the voltage value of the imaging element, corresponding to the amount of incident light detected. This process advantageously removes noise known as ‘kTC’ noise.
In general, the pixel reset signal PR, the activation signal SL, and the row readout signal RR are supplied to all pixels belonging to the same row. However, an image may have a large contrast between its dark and bright areas. For optimum image reconstruction, the pixels or group of pixels corresponding to dark areas of the image should have longer charge accumulation times, and the pixels or groups of pixels corresponding to bright areas should have shorter charge accumulation times.
To this end, U.S. Pat. No. 7,969,490 discloses the provision, in each imaging element U, of a selection transistor ST associated with a pixel P as shown in FIG. 1. The selection transistor ST has a drain D receiving a column selection signal Sy, a gate G driven by a row selection signal Sx, and a source S supplying the activation signal SL to the gate G of the transfer transistor TT.
When the row selection signal Sx and the column selection signal Sy are both at logic 1, corresponding to positive voltages, the activation signal SL is driven to a positive voltage value. The transistor TT is set in the conducting state. Otherwise, if the row and/or column selection signals Sx, Sy are at logic 0, the transfer transistor TT remains set in the blocked state.
During an image capture cycle, all pixels of a row begin the charge accumulation period at the same time. Certain pixels of the row are then individually reset at later times to re-start their charge accumulation periods for shorter times. The contrast of the image may therefore be adjusted on an individual pixel basis. The charge accumulation phase then ends at the same time for all pixels of the row.
Another phenomenon that may affect the image quality is known as “dark current.” Dark current is a current generated in the photosensor even when no incident light is received. It is known that dark current can be reduced by applying a negative voltage to the gate of the transfer transistor TT during the charge accumulation phase. In this manner, electrons that would normally contribute to the dark current recombine with holes and are neutralized. Nevertheless, the imaging element of FIG. 1 does not allow the application of a negative voltage to the gate of the transfer transistor TT.
U.S. Pat. No. 7,518,168 discloses a way to apply a negative voltage to the gates of all the transfer transistors TT of all imaging elements of a row. However, this patent does not disclose an individual selection of the imaging elements, whereas U.S. Pat. No. 7,969,490 does not provide dark current prevention.